THYRISTOR GATE CHARACTERISTICS
The forward gate characteristics of a thyristor are shown in Fig. 4.9 in the form of a graph between gate voltage and gate current. Here positive gate to cathode voltage Vg and positive gate to cathode current Ig represent dc values. As gate-cathode circuit of a thyristor is a p-n junction, gate characteristics of the device are similar to that of a diode. For a particular type of SCRs, Vg-Ig characteristic has a spread between two curves 1 and 2 as shown in Fig. 4.9. This spread, or scatter, of gate characteristics is due to difference in the low doping levels of p and n layers. The gate trigger circuitry must be suitably designed to take care of this unavoidable scatter of characteristics. In Fig. 4.9, curve 1 represents the lowest voltage values that must be applied to turn-on the SCR. Curve 2 gives the highest possible voltage values that can be safely applied to gate circuit.
Each thyristor has maximum limits as Vgm for gate voltage and Igm for gate current. There is also rated (average) gate power dissipation Pgav specified for each SCR. These limits should not be exceeded in order to avoid permanent damage of junction J3, Fig. 4.3. There are also minimum limits for Vg and Ig for reliable turn-on, these are represented by oy and ox and respectively in Fig. 4.9. As stated before, if Vgm , Igm and Pgav are exceeded, the thyristor can be destroyed. This shows that preferred gate drive area for an SCR is bcdefghb as shown in Fig. 4.9.
A non-triggering gate voltage is also prescribed by the manufacturers of SCRs. This is indicated by oa in Fig. 4.9. If firing circuit generates positive gate signal prior to the desired instant of triggering the SCR, it should be ensured that this unwanted signal is less than the non-triggering gate voltage oa. At the same time, all spurious or noise signals should be less than the voltage oa.
The design of the firing circuit can be carried out with the help of Figs. 4.10 and 4.11. In Fig. 4.10 (a) is shown a trigger circuit feeding power to gate-cathode circuit. For this circuit,
ES = Vg + IgRS ……..(4.1a)
where Es = gate source voltage
Vg = gate-cathode voltage
Ig = gate current
and Rs = gate-source resistance
The internal resistance Rs of trigger source should be such that current (Es/Rs) is not harmful to the source as well as to the gate circuit when SCR is turned on. In case Rs is low, an external resistance in series with Rs must be connected.
A resistance R1 is also connected across gate-cathode terminals, Fig. 4.10 (b), so as to provide an easy path to the flow of leakage current between SCR terminals. If Igmn and Vgmn are the minimum gate current and gate voltage to turn-on SCR, then it is seen from Fig. 4.10. (b) that current through R1 is Vgmn/R1 and the trigger source voltage Es is given by
Es= [Igmn + Vgmn/R1 ] Rs + Vgmn …(4.1b)
For low-power circuits, operating point is obtained by utilizing the source V-I characteristic and the device V-I characteristic. In view of this, for selecting the operating point for the circuit of Fig. 4.10, a load line of the gate source voltage Es = OA is drawn as AD in Fig. 4.11. Here OD = trigger circuit short circuit current =ES/RS. Let us consider a thyristor whose Vg-Ig characteristic is given by curve 3. Intersection of load line AD and Vg-Ig curve 3 gives the operating point S. Thus, for this SCR, gate voltage =PS and gate current = OP. In order to minimise turn-on time and jitter (unreliable turn-on), the load line and hence the operating point S, which may change from S1 to S2, must be as close to the Pgav curve as possible. At the same time, the operating point S must lie within the limit curves 1 and 2. The gradient of the load line AD (= OA/OD) will give the required gate source resistance Rs The minimum value of gate source series resistance is obtained by drawing a line AC tangent to Pgav curve
Gate drive requirements in terms of continuous dc signal can be obtained from Fig. 4.11. However, it is common to use a pulse to trigger a thyristor. For pulse widths beyond 100 µsec, the dc data apply . For pulse widths less than 100 µsec, magnitudes of gate voltage and gate current can be increased.
As stated before, thyristor is considered to be a charge controlled device. Thus, higher the magnitude of gate current pulse, lesser is the time to inject the required charge for turning-on the thyristor. Therefore, SCR turn-on time can be reduced by using gate current of higher magnitude. It should be ensured that pulse width is sufficient to allow the anode current to exceed the latching current. In practice, gate pulse width is usually taken as equal to, or greater than, SCR turn-on time. If T is the pulse width as shown in Fig. 2.10 (a), then
T > t on
With pulse triggering, greater amount of gate power dissipation can be allowed ; this should, however, be less than the peak instantaneous gate power dissipation Pgm as specified by the manufacturers. Frequency of firing (or pulse width) for trigger pulses can be obtained by taking pulse of (i) amplitude Pgm (ii) pulse width T and (iii) periodicity T1. Therefore,
Pgm T/ T1 > Pgav or Pgm .T. f > Pgav
Pgav / f T < Pgm
where f = 1/ T1 = frequency of firing, or pulse repetition rate, in Hz,
T = pulse width in sec
In the limiting case, Pgav / f T = Pgm or f = Pgav /T. Pgm
A duty cycle is defined as the ratio of pulse-on period to periodic time of pulse. In Fig. 4.12 (a), pulse-on period is T and periodic time is T1. Therefore, duty cycle δ is given by
δ = T/ T1 = f T
From Eq. 4.2 (a), Pgav / δ < Pgm or Pgav / δ = Pgm …(4.2 b)
Sometimes the pulses of Fig. 4.12 (a) are modulated to generate a train of pulses as shown in Fig. 4.12 (b). This technique of firing the thyristor is called high-frequency carrier gating. The advantages offered by this method of firing the SCRs are lower rating, reduced dimensions and therefore an overall economical design of the pulse transformer needed for isolating the low power circuit from the main power circuit.
For an SCR, Vam and Igm are specified separately. If both of these are used for pulse firing,then Pgm may be exceeded and the thyristor would be damaged. For example, GE-C35 thyristor has Vgm = 10 V and Igm = 2 A. If both these limits are placed on C35, the power dissipation is 20 W. But this is far excess of the specified Pgm = 5 W. It should be ensured that (pulse voltage amplitude) (pulse current amplitude) < Pgm.
There is also prescribed a peak reverse voltage (gate negative with respect to cathode) that can be applied across gate-cathode terminals. Any voltage signal, given by the trigger circuit (or by any interference), exceeding this prescribed limit of about 5 to 20 V may damage the gate circuit. For preventing the occurrence of such hazards, a diode is connected either in series with the gate circuit or across the gate-cathode terminals as shown in Fig. 4.12 (c). Diode across the gate-cathode terminals, called clamping diode, prevents the gate-cathode voltage from becoming more than about 1 V. Diode in series with gate circuit prevents the flow of negative gate source current from becoming more than small reverse leakage current.
The magnitude of gate voltage and gate current for triggering an SCR is inversely proportional to junction temperature. Thus, at very low temperatures, gate voltage and gate current must have high values in order to ensure turn-on. But Pgm should not be exceeded in any case.
The resistor Rl , connected across gate-cathode terminals, Fig. 4.10 (b), also serves to bypass a part of the thermally-generated leakage current across junction J2 when SCR is in the forward blocking mode ; this improves the thermal stability of SCR.